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[CSharp] eepromWr

Description: FTDIUartDe0nano. C# code to comunicate with FTDI USB/serial interface and UART on FPGA. The target is to read write and EEPROM.
Platform: | Size: 193536 | Author: vivera28 | Hits:

[Other] usb_ctl

Description: CH372 USB芯片 采用Verilog语言，实现FPGA与上位机通信，按键触发FPGA向上位机传数，USB测试软件向FPGA传数-CH372 USB chip using Verilog language, to achieve FPGA and PC communications, key trigger FPGA pass up crew numbers, USB test software to pass several FPGA
Platform: | Size: 3072 | Author: zhenli | Hits:

[VHDL-FPGA-Verilog] DE2_USB_API

Description: 基于altera DE2开发板的USB应用程序，可以实现对FPGA的各项控制，包括输入数据到SRAM中，更换VGA显示器显示的图片等-Based on altera DE2 development board USB application process can be achieved with the control of the FPGA, including the input data to the SRAM, the replacement of VGA display pictures, etc.
Platform: | Size: 2023424 | Author: 叶志远 | Hits:

[VHDL-FPGA-Verilog] usb1029

Description: 实现FPGA对Cypress公司的68013A款的USB芯片应用于SLAVEFIFO的读操作，使用verilog语言编写，Q2开发环境。-FPGA to realize the company s 68013A paragraph Cypress USB chip used SLAVEFIFO read operation, using verilog language, Q2 development environment.
Platform: | Size: 403456 | Author: | Hits:

[matlab] fft_ly

Description: 采用MATLAB实现定点的FFT运算，但是仿真硬件结构的IP核调用以及误差产生模式，用于仿真FPGA实现FFT运算的效果和误差来源。-FPGA to realize the company s 68013A paragraph Cypress USB chip used SLAVEFIFO read operation, the fixed-point implementation using MATLAB FFT operation, but the hardware structure of the IP core simulation calls and error generation model for simulating the effects of FPGA implementation and FFT computation sources of error.
Platform: | Size: 2048 | Author: | Hits:

[VHDL-FPGA-Verilog] YJ_EP4

Description: 与Cpress CY8013所对应的 FPGA端的开发 使用NIOSII NIOSII 连续往USB FIFO 端点里灌数据 上位机不断的接收 陪和我的上位程序可以达到30Mbyte/s 需要上位机程序的去搜索TestUSBSpeedMFCNovember -upload-And Cpress CY8013 corresponding end FPGA development using NIOSII NIOSII continuous irrigation to USB FIFO endpoint data in the host computer receives constantly accompany and my host program can reach 30Mbyte/s PC program needs to search TestUSBSpeedMFCNovember-upload
Platform: | Size: 25570304 | Author: kn | Hits:

[VHDL-FPGA-Verilog] wishbone

Description: Wishbone规范具有如下特点:简单、紧凑，需要很少的逻辑门 完整的普通数据据传输总线协议，包括单个读写、快传输、读一修改一写周期、事件周期 数据总线宽度可以是8-64位 支持大端(big-endian)和小端(litle-endian)，接口自动完成两者之间的转换。支持存储器映射、FIFO存储器、交叉互联 握手协议，允许速率控制 可以达到每个时钟周期进行一次数据传输 支持普通周期结束、重试结束、错误结束等总线周期形式 支持用户自定义的标志:采用MASTER/SLAVE体系结构 支持多点进程(Multi-MASTER):仲裁算法用于定义 支持各种各样的IP核互联，包括USB、双向总线、复用器互联等 同步逻辑设计 非常简单的时序标准 与硬件实现技术无关(FPGA, ASIC等) 与设计工具无关。 相对于其他的IP核接口规范来说，Wishbone接口规范具有简单、开放、高效、利于实现等特点而且完全免费，并没有专利保护。基于上述优点，因此采用Wishbone总线进行接口设计。本文对Wishbone总线接口的设计参考了OpenCore上的有关设计。- Wishbone specification has the following characteristics : a simple , compact, and requires very little logic gates complete common data bus data transfer protocols, including single reader , fast transmission, read-modify- write cycle, the event cycle data bus width can be 8-64 bit support big-endian (big-endian) and the small end (litle-endian), the interface automatically convert between the two. Support memory mapping , FIFO memory , cross interconnection handshake protocol that allows rate control every clock cycle to achieve a data transfer support normal cycle ends , retry the end , wrong end of the bus cycle and other forms support for user-defined flags : The MASTER/SLAVE architecture supports multi- process (Multi-MASTER): arbitration algorithm is used to define support a variety of IP cores interconnected , including USB, bi-directional bus , multiplexer interconnection , etc. synchronous logic design very simple timing standards technology-indepe
Platform: | Size: 12288 | Author: 程浩武 | Hits:

[VHDL-FPGA-Verilog] 17_usb_device

Description: 基于NIOS II的USB驱动设计，在FPGA平台上加入NIOS处理器以及需要的ip构成嵌入式系统实现USB数据传输-NIOS II design is based on the USB drive, and the need to join NIOS processor on an FPGA platform ip constitute embedded systems USB Data Transfer
Platform: | Size: 3072 | Author: ddiao | Hits:

[VHDL-FPGA-Verilog] UsbFPGAdemo

Description: FPGA底层的USB接口芯片的驱动，用于向上位机传送数据。-Driving USB interface chip FPGA bottom, used to transmit data to the host computer.
Platform: | Size: 2196480 | Author: 张仰望 | Hits:

[VHDL-FPGA-Verilog] DE2_NIOS_HOST_MOUSE_VGA

Description: 本代码为DE2开发板例程源码（EP2C35F672C6），项目基于quartus II 9.0（随板光盘为7.2版本以下，在9.0版以上编译会报错）。本项目实现一个USB画笔功能，通过FPGA控制USB口，USB口接上鼠标，通过XGA口外界显示设备，实现显示设备对鼠标移动轨迹的显示。-In this demonstration, we implement a Paintbrush application by using a USB mouse as the input device.This demonstration uses the device port of the Philips ISP1362 chip and the Nios II processor to implement a USB mouse movement detector. We also implemented a video frame buffer with a VGA controller to perform the real-time image storage and display.
Platform: | Size: 2547712 | Author: chenxin | Hits:

[VHDL-FPGA-Verilog] TestProject

Description: 用fpga + usb ,fpga 用ep3c10e144 , usb 用釙68013日. 使用nios dma 傳輸數據至cy7c68013 , 經usb 到電腦-it use altera cyclone iii ep3c10e144 and cypress cy7c68013a to pc using nios dma to transmit data to pc via cy7c68013
Platform: | Size: 29622272 | Author: 梁定宇 | Hits:

[source in ebook] syn_rd_wr_fifo

Description: 该代码实现了FPGA对USB芯片68013的读写，语言是VERLOD，试验通过。-The code to achieve the FPGA read and write 68013 on the USB chip, the language is VERLOD, through the test.
Platform: | Size: 4414464 | Author: MR.JHY | Hits:

[VHDL-FPGA-Verilog] USB_save

Description: 这是基于FPGA的USB通讯程序。通过在quartus中建立SOPC，建立PIO口，并在NIOS中写驱动和寄存器等，实现USB通信。经检验，该程序通信正常。-This is FPGA-based USB communication program. By establishing the quartus in SOPC, establish PIO mouth and NIOS to write drivers and registers, realize USB communications. Upon examination, the program can communicate.
Platform: | Size: 18978816 | Author: 周燕 | Hits:

[SCM] MCU

Description: 单片机开发源码，用于实现FPGA数据向单片机发送数据，转换成USB协议后传输到电脑上-MCU development source for implementing FPGA data to the microcontroller to send data, convert the USB protocol transmitted to the computer
Platform: | Size: 139264 | Author: 刘万利 | Hits:

[VHDL-FPGA-Verilog] 6_USB_to_SDHC_Lab

Description: 基于altera公司MAX10型FPGA的usb至sdhc通信的调试程序-Altera company based debugger MAX 10 type of FPGA to sdhc usb communication
Platform: | Size: 2832384 | Author: qiqi | Hits:

[VHDL-FPGA-Verilog] USB_send_recive

Description: 完全用verliog写的FPGA和CH372与电脑USB设备通信。可以和电脑收发数据，已经测试成功，如有疑问留言，程序可能有点乱，-Written entirely in verilog FPGA and CH372 USB devices to communicate with the computer. And computers can send and receive data, it has been tested successfully, if in doubt leave a message, the program may be a bit messy,
Platform: | Size: 5426176 | Author: 高政 | Hits:

[Other systems] butterflylight_latest.tar

Description: The Butterfly Light is an open source, modular FPGA development board. It is comprised of the USB Cocoon and the Spartan 3E Cocoon which paired together create the Butterfly Light FPGA development board. The Butterfly Light is best suited for developers who prefer to create their own daughterboards instead of utilizing the Wing peripheral system. The Butterfly Light exposes the maximum amount of I/O of all available Butterflies. It is also well suited for use with the Logic Analyzer software which implements a 100Mhz, 32 channel Logic Analyzer.-The Butterfly Light is an open source, modular FPGA development board. It is comprised of the USB Cocoon and the Spartan 3E Cocoon which paired together create the Butterfly Light FPGA development board. The Butterfly Light is best suited for developers who prefer to create their own daughterboards instead of utilizing the Wing peripheral system. The Butterfly Light exposes the maximum amount of I/O of all available Butterflies. It is also well suited for use with the Logic Analyzer software which implements a 100Mhz, 32 channel Logic Analyzer.
Platform: | Size: 198656 | Author: Joe | Hits:

[Home Personal application] utosnet_latest.tar

Description: The uTosNet framework aims at providing a very fast method for interfacing physical components, such as motor drivers, ADCs, encoders, and similar, to applications on a PC. The framework is based on the Node-on-Chip architecture (link to paper coming). It works by utilizing a dual-port BlockRam in the FPGA, with one port exposed to access the PC (through uTosNet) and the other port exposed to access user-defined modules. This allows easy and generic storage of process variables. Currently two versions of uTosNet are supported: PC side USB converter chip UART FPGA PC side Ethernet Digi Connect ME 9210 microcontroller module SPI FPGA-The uTosNet framework aims at providing a very fast method for interfacing physical components, such as motor drivers, ADCs, encoders, and similar, to applications on a PC. The framework is based on the Node-on-Chip architecture (link to paper coming). It works by utilizing a dual-port BlockRam in the FPGA, with one port exposed to access the PC (through uTosNet) and the other port exposed to access user-defined modules. This allows easy and generic storage of process variables. Currently two versions of uTosNet are supported: PC side USB converter chip UART FPGA PC side Ethernet Digi Connect ME 9210 microcontroller module SPI FPGA
Platform: | Size: 7190528 | Author: Joe | Hits:

[CSharp] myUSB_c20150901

Description: 通过usb接口给FPGA下载文件 usb接口芯片为ft232h 界面软件-Through the usb interface to download the file interface software
Platform: | Size: 5890048 | Author: sss | Hits:

[Delphi VCL] nexys4-ddr_sw_demo

Description: The Nexys4 DDR board is a complete, ready-to-use digital circuit development platform based on the latest Artix-7™ Field Programmable Gate Array (FPGA) Xilinx® . With its large, high-capacity FPGA (Xilinx part number XC7A100T-1CSG324C), generous external memories, and collection of USB, Ethernet, and other ports, the Nexys4 DDR can host designs ranging from introductory combinational circuits to powerful embedded processors. Several built-in peripherals, including an accelerometer, temperature sensor, MEMs digital microphone, a speaker amplifier, and several I/O devices allow the Nexys4 DDR to be used for a wide range of designs without needing any other component-The Nexys4 DDR board is a complete, ready-to-use digital circuit development platform based on the latest Artix-7™ Field Programmable Gate Array (FPGA) Xilinx® . With its large, high-capacity FPGA (Xilinx part number XC7A100T-1CSG324C), generous external memories, and collection of USB, Ethernet, and other ports, the Nexys4 DDR can host designs ranging from introductory combinational circuits to powerful embedded processors. Several built-in peripherals, including an accelerometer, temperature sensor, MEMs digital microphone, a speaker amplifier, and several I/O devices allow the Nexys4 DDR to be used for a wide range of designs without needing any other component
Platform: | Size: 1024 | Author: yaseenn | Hits:
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